This invention relates to a semiconductor device structure and method wherein a power semiconductor device is employed as a substrate upon which other electronic components are disposed.
In the past, multi-chip power circuits have been designed in which a power semiconductor device was employed as a substrate upon which low voltage control circuitry was mounted. Previous techniques for galvanically isolating the power device from its associated control circuitry have achieved galvanic isolation on the order of 500 volts. The use of passivation materials having greater isolating characteristics has been problematic in that other characteristics of these materials have limited the manner in which the forward voltage drop of the power device may be reduced. For example, the low temperature tolerance of some passivation materials have made it impossible to perform high temperature processing (e.g., furnace anneal) of the power device to ensure a low voltage drop through the device.
Therefore, because of the relatively low galvanic isolation achieved by previous multi-chip techniques, there is a need for a multi-chip structure and method which achieve greater isolation between a power semiconductor device substrate and its associated low voltage control circuitry.